The present invention relates to the field of digital communications.
More particularly, it relates to the conditioning of a sequence of modulation symbols for a modulation scheme which provides different bits constituting a modulation symbol with different levels of bit error probability.
An important class of such modulation schemes is made of quadrature amplitude modulations (QAM). These modulation schemes have become popular because of their performance in terms of bandwidth. Most often, they accept input symbols consisting of n bits, with n integer, i.e. the symbols may have N=2n states. Such modulation of N-ary symbols is referred to as N-QAM.
In the following, 16-QAM will be more particularly considered (n=4). However, it will be appreciated that the discussion is also applicable to any N-QAM scheme.
In certain systems, a QAM modulator is associated with an encoder which delivers bits of different importance for the receiver.
For example, such coder may be a systematic error correction coder making use of turbocodes (see C. Berrou et al., “Near Shannon Limit Error-Correcting Coding and Decoding: Turbo Codes”, Proc. of IEEE ICC'93, Geneva, Switzerland, May 1993, pp. 1064-1070). A turbocoder delivers on the one hand systematic bits and on the other hand parity bits, and it is well known that the systematic bits have a higher importance than the parity bits for the receiver's ability to correct transmission errors.
In “Turbo Trellis Coded Modulation for Fading Channels” (Proc. of IEEE VTC Spring'00, June 2000, Tokyo, Japan, pp. 2059-2063), J. Yuan et al. propose to map the bit output of a turbocoder onto the N-ary input symbols of a N-QAM modulator. The authors suggest that the systematic bits output by the turbocoder should be mapped to the bit positions having the lowest probability of transmission error within the N-ary symbols, while the parity bits are mapped to the bit positions of higher transmission error probability.
Such an association of a turbocoder and a QAM modulator has been proposed for the transmission chain used in the HSDPA service in UTRAN networks. HSDPA is an acronym for “High Speed Downlink Packet Access”. UTRAN is an acronym for “UMTS Terrestrial Radio Access Network”. UMTS (“Universal Mobile Telecommunication System”) is a third generation cellular radio communication system which is being standardized by the 3rd Generation Partnership Project (3GPP).
The UMTS HSDPA service makes use of so-called HS-DSCH channels (“High Speed-Downlink Shared Channels”) in which the user data are encoded by means of a rate ⅓ turbocode. The modulation is 16-QAM.
However, a problem encountered in this system is that some operations are carried out between the output of the turbocoder and the input of the QAM modulator. These operations include a variable rate puncturing, or rate matching, followed by an interleaving. The rate matching is coupled with a hybrid ARQ (“Automatic Repeat reQuest”) mechanism with incremental redundancy (IR). Accordingly, the processing required at the output of the interleaver to map the systematic and parity bits onto the relevant bit positions of the QAM symbols is very complicated since a very large number of variable puncturing and incremental redundancy configurations have to be taken into account downstream of the shuffling caused by the interleaver.
An object of the present invention is to overcome these difficulties by providing an improved method of constructing a sequence of modulation symbols, which is relatively easy to implement, even for blocks of coded information bits having various structures.